FIG. 2 shows a spread spectrum receiver using a convolver as a correlator. In the drawing, reference numeral 1 refers to a convolver, 2 to an envelope detecting circuit, 3 to a high-speed integrating circuit, e.g. a known PDI (Post-Detection-Integration) circuit, 4 to a data demodulating circuit, and 5 to an integral operation timing signal generating circuit including a frequency dividing circuit, etc.
One of inputs of the convolver 1 is supplied with a received signal S1 which is a spread-spectrum signal obtained by multiplication of a spreading signal and an information signal and transmitted from a spread spectrum transmitter (not shown). The other input of the convolver 1 is supplied with a reference signal S2 produced from a spreading code including a PN code, etc. A correlation output from the convolver 1 is detected by the envelope detecting circuit 2, and a correlation spike signal S3 having a sharp waveform shown in FIG. 3 is outputted and used to perform code synchronization, data demodulation and other operations.
In FIG. 3, T1 equals one period length of a clock signal for generating a spreading code (hereinafter called "PN clock"), and T2 is the period at which correlation spike signals are outputted. When the code length of the spreading code is N chips, the following relationship is established: ##EQU1##
FIG. 3 shows a waveform of a correlation spike signal in an ideal condition. Actually, however, such spread spectrum communication is effected in a multi-path fading or other bad condition, and the correlation spike signal shows a waveform as shown, for example, in Figure 4. In this circumstance, in order to ensure normal code synchronization, data demodulation and other operations also when the correlation spike signal exhibits such an undesirable waveform, a countermeasure is usually taken by integrating the correlation spike signal S3 having the waveform of Figure in the PDI circuit, i.e. in the high-speed integrating circuit 3 in FIG. 2, producing a signal S4 having the waveform of FIG. 5, applying it to the data demodulating circuit and obtaining a data output S5.
In order to obtain a high-speed integration signal output shown in FIG. 5 by integrating at a high-speed the correlation spike signal dispersed by multi-path fading as shown in FIG. 4, the integrating time must be longer (mT1) than T1 (m is a natural number). If high-speed integration signal outputs are obtained every mT1 interval, integration timing signals can be produced conveniently by a frequency dividing circuit having a simple arrangement configured to frequency-divide a PN clock signal into integer fractions.
When code synchronization, data demodulation or other operation is performed using such a high-speed integration signal output, the correlation spike signal generating timing and the timing of producing a high-speed integration signal output corresponding to the correlation spike signal must be synchronized as shown in FIG. 6 (example of m=2).
More specifically, the following relationship is required: ##EQU2## where m and n are natural numbers satisfying mn.gtoreq.2.
By comparing equations (1) and (2), a necessary condition the code length N (chips) of the spreading code is obtained, and N must satisfy: EQU N=2mn (3)
That is, the spreading code must have an even number of chips.
However, when a PN code having one period length Nm expressed by equation (4) is used (for example, maximum length linearly sequentially occurring code) as the spreading code, the code length of the spreading code becomes one period length Nm of the PN code. Apparently, this does not satisfy equation (3) as follows: EQU Nm=2.sup.i -1 (odd number) (4)
where i is 3 or larger integer.
As explained above, when a PN code is used as the spreading code and the one period length of the PN code is used in the original form as the code length of the spreading code in a spread spectrum receiver, the circuit arrangement is large-scaled because:
(i) the circuit requires an additional complicated frequency divider to produce a timing signal for operation of the high-speed integration circuit; and PA1 (ii) the circuit requires a clock signal generating circuit for generating a clock signal different in frequency from the PN clock signal for generation of the PN codes.